1. Field of Invention
This invention relates in general to semiconductor memories and in particular to burn-in testing of DRAM (dynamic random access memory) and FeRAM (ferroelectric random access memory) memory chips.
2. Description of Related Art
With the increased density and complexity of semiconductor devices, the elements of the circuitry are becoming increasingly smaller and more prone to defects. Smaller sized defects are increasingly more important as semiconductor device elements become smaller. The use of burn-in testing to sort out devices with defects is important for detecting defective units, and a mainstay of semiconductor memory processing.
In U.S. Pat. No. 5,657,282 (Lee) a stress circuit and a method of applying a stress voltage is described. During test a first and second stress voltage is applied to physically adjacent word lines, and the state of a selected memory cell is sensed. In U.S. Pat. No. 5,467,356 (Choi) a burn-in enable circuit and a burn-in test method is shown. A high external voltage exceeding the external power voltage is applied to a semiconductor memory device that is detected by a burn-in enable circuit and causes a high stress voltage to be applied to all access transistors during burn-in. In U.S. Pat. No. 5,357,193 (Tanaka et al.) is described a memory device with a high voltage stress applying circuit and which reduces the number of test pads required on the memory chip. In U.S. Pat. No. 5,155,701 (Komori et al.) a method is described for testing inferior data retention of a defective EPROM memory cell.
In DRAM testing as with other high density semiconductor devices, improving the throughput of the semiconductor process is important to reducing manufacturing cost. Being able to screen out defective chips early in the process reduces the load on additional required process steps. Detecting defective memory chips at the wafer level provides a means by which the throughput of the manufacturing process can be improve.